1. Field of the Invention
The invention relates to methods for mapping or exploring mappings of applications on a multiprocessor platform or system.
2. Description of the Related Technology
Certain inventive aspects relate to the disclosure of the U.S. Pat. No. 6,609,088 and the European patent application no. EP-0974906 on ‘System-level power optimization of data storage and transfer’, which are herewith incorporated by reference, but adapted for use in a multiprocessor context.
The use of a memory hierarchy for optimizing at least power consumption of essentially digital systems, performing data-dominated applications, is known. The idea of using a memory hierarchy to minimize the power consumption of the essentially digital systems is based on the fact that memory power consumption depends primarily on the access frequency and the size of the memories. Power savings can be obtained by accessing heavily used data from smaller memories instead of from large background memories. Such an optimization requires architectural transformations that consist of adding layers of smaller and smaller memories to which frequently used data can be copied. Memory hierarchy optimization introduces copies of data from larger to smaller memories in the data flow graph. This means that there is a trade-off involved here: on the one hand, power consumption is decreased because data is now read mostly from smaller memories, while on the other hand, power consumption is increased because extra memory transfers are introduced. Moreover, adding another layer of hierarchy can also have a negative effect on the area and interconnect cost, and as a consequence also on the power consumption because of the larger capacitance involved. The memory hierarchy design task has to find the best solution for this trade-off. Some custom memory hierarchy experiments on real-life applications can be found in literature but often the search space, being the potential memory hierarchies which can be exploited, is not extensively examined. No systematic exploration method for deciding on which memory hierarchy is optimal with respect to power consumption of the digital system is known.
Data reuse exploration, memory hierarchy layer assignment, and the concept of block transfers in single processor context are known from [S. Wuytack, J. P. Diguet, F. Catthoor, H. De Man: “Formalized methodology for data reuse exploration for low-power hierarchical memory mappings”, IEEE Trans. on VLSI Systems, vol. 6, no. 4, pages 529-537, December 1998], [T. Van Achteren, G. Deconinck, F. Catthoor, R. Lauwereins: “Data Reuse Exploration Methodology for Loop-dominated Applications”, IEEE/ACM Design Automation and Test Conference, Paris, France, Mar. 4-8, 2002], [I. Issenin, E. Brockmeyer, M. Miranda, N. Dutt: “Data reuse technique for software-controlled memory hierarchies”, In Design Automation and Test in Europe, February 2004.], [Erik Brockmeyer, Miguel Miranda, Henk Corporaal, Francky Catthoor: “Layer Assignment Techniques for Low Energy in Multi-layered Memory Organizations”, Proc. 6th ACM/IEEE Design and Test in Europe Conf. 2003], [Minas Dasygenis, Erik Brockmeyer, Bart Durinck, Francky Catthoor, Dimitrios Soudris, Antonios Thanailakis: “A Memory Hierarchical Layer Assigning and Prefetching Technique to Overcome the Memory Performance/Energy Bottlenecks”, 2005, 946-947].